`include "PRV564Config.v"
`include "PRV564Define.v"

module RegFile(
	input wire 			clk         ,
	input wire 			wr_en      ,
	input wire [4:0] 	rd0_addr    ,
	input wire [4:0] 	rs1_addr    ,
	input wire [4:0]	rs2_addr    ,
	input wire [63:0] 	rd0_data    ,
	output wire [63:0] 	rs1_data    ,
	output wire [63:0] 	rs2_data	 
	`ifdef DEBUG_FLAG    
		,output wire [64*32-1:0]snapshot
	`endif
) ;
	reg [63:0] REGFILE [31:1];
	wire w_en ;
`ifdef DEBUG_FLAG  
	genvar i;
	assign snapshot[63:0]=65'h0000_0000_0000_0000;
	generate for(i=1;i<32;i=i+1) 
		begin : U
			assign snapshot[(64*(i+1))-1:64*i]=REGFILE[i];
		end
	endgenerate
`endif
assign w_en = ( rd0_addr == 5'b00000 ) ? ( 1'b0 ) : ( wr_en ) ;


always @ ( posedge clk ) begin
	if ( w_en ) begin
		REGFILE [ rd0_addr ] <= rd0_data ;
	end
end

assign rs1_data = (rs1_addr==5'b0)?64'b0 : REGFILE [ rs1_addr ] ;
assign rs2_data = (rs2_addr==5'b0)?64'b0 : REGFILE [ rs2_addr ] ;

endmodule

